1. Field of the Invention
The present invention relates to a boost voltage generating circuit, and more particularly to a boost voltage generating circuit for producing a boost potential for a word line of a semiconductor memory device or of a substrate potential for a semiconductor integrated circuit.
2. Description of the Related Art
An example of the conventional boost voltage generating circuit of the kind to which the present invention relates is shown in FIG. 1A and the waveforms obtained at various points therein are shown in FIG. 1B.
The conventional boost voltage generating circuit referred to above is constituted by a timing control circuit 1 and a boost voltage producing section 2. The timing control circuit 1 outputs a first control signal .PHI.1 and a second control signal .PHI.2 respectively through an output node of an inverter IV1 and an output node of an inverter IV2. The first control signal .PHI.1 becomes a power supply potential (V.sub.CC) level and a reference potential (ground potential) level in a predetermined cycle, and the second control signal .PHI.2 becomes a power supply potential level for a predetermined period within the period of the reference potential level of the first control signal .PHI.1 and becomes a reference potential level outside the period of the power supply potential level. The boost voltage producing section 2 includes first and second capacitor elements C1 and C2 which receive respectively the first and second control signals .PHI.1 and .PHI.2 at their first ends; a first N-channel field effect transistor Q1 in which one of a source and a drain is connected to the power supply potential terminal (V.sub.CC), the or(her of the source and the drain is connected to a second end of the first capacitor element C1, and a gate is connected to the second end of the second capacitor element C2; a second N-channel transistor Q2 in which one of a source and a drain is connected to the power supply potential terminal V.sub.CC, the other of the source and the drain is connected to the second end of the second capacitor element C2, and a gate is connected to the second end of the first capacitor element C1; a third N-channel transistor Q3 in which one of a source and a drain, and a gate are connected to the second end of the first capacitor element C1, and the other of the source and the drain is connected to a boost potential output terminal V.sub.OUT (V.sub.OUT also representing the boost potential); a fourth N-channel transistor Q4 in which one of a source and a drain, and a gate are connected to the second end of the second capacitor element C2, and the other of the source and the drain is connected to the boost potential output terminal V.sub.OUT ; and a third capacitor element C.sub.O having a large capacitance which is connected between the boost potential output terminal V.sub.OUT and the reference potential terminal.
The operation of the above explained boost voltage generating circuit is as follows.
When the control signal .PHI.1 is at the power supply potential level V.sub.CC and the control signal .PHI.2 is at the ground potential level (0 V), the transistor Q2 turns ON so that the node N2 at the second end of the second capacitor element C2 is charged and becomes the power supply potential V.sub.CC. Also, if the node N1 at the second end of the first capacitor element C1 is at a level higher than V.sub.OUT +V.sub.T (V.sub.T being the threshold voltage of the transistor), the current flows from the node N1 to the boost potential output terminal V.sub.OUT through the transistor Q3 and thus the boost potential V.sub.OUT is raised to a level higher than the power supply potential V.sub.CC.
Next, contrary to the above, when the control signal .PHI.1 turns to the ground potential level and the control signal .PHI.2 turns to the power supply potential level, the potential at the node N2 rises close to 2 V.sub.CC whereby the transistor Q1 becomes ON and the node N1 is charged up to the level of the power supply potential V.sub.CC. Also, the charges are supplied to the boost potential output terminal V.sub.OUT through the transistor Q4.
The above operation is repeated and, after being smoothed by the capacitor element C.sub.O having a large capacitance, the boost voltage V.sub.OUT is raised to a potential higher than the power supply potential V.sub.CC.
The boost voltage V.sub.OUT thus obtained is used for such purposes as for select-level driving of word lines of a semiconductor memory device. Also, when the P-channel transistors are employed and the potentials at various points are reversed, it is possible to obtain the substrate potential to be applied to the substrate of a semiconductor integrated circuit.
In the boost voltage generating circuit described above, since the charges of the capacitor element C1 are supplied to the boost potential output terminal V.sub.OUT through the transistor Q3 when the control signal .PHI.1 is at the power supply potential level V.sub.CC, the level at the node N1 gradually lowers starting from about 2 V.sub.CC as shown in FIG. 1B. Therefore, the ON-resistance of the transistor Q3 whose gate is directly connected to the node N1 becomes greater, resulting in the lowering of the current driving capability so that, although it is possible to boost the boost potential V.sub.OUT almost to 2 V.sub.CC minus V.sub.T, the current supply capability largely drops once the boost potential V.sub.OUT is set to a high level.